1. Field of the Invention
The present invention relates to a data processor such as a microcomputer having a peripheral circuit, and a system clock oscillator for generating a system clock signal, and capable of operating in a power saving mode for reducing power consumption.
2. Description of Related Art
Recently, data processors such as microcomputers, above all, single-chip microcomputers have been widely applied to portable equipment like notebook PCs and video cameras, resulting in reduction in their size and power consumption. In particular, there is a growing demand for power saving of equipment using a battery as its power supply to further lengthen its operation time.
In CMOS single-chip microcomputers, their consumed current will be reduced by decreasing the operation frequency because the former is proportional to the latter. However, the operation frequency cannot be reduced if a high-rate operation is required.
As an alternative to the foregoing, the power saving can be achieved by applying sleep mode in which the oscillator of a single-chip microcomputer is stopped while it does not carry out processing. Thus, it operates only when some processing is required.
In the power saving using the sleep mode, however, the single-chip microcomputer cannot operate its embedded peripheral circuits such as an A/D converter while the oscillator is being stopped. To operate the A/D converter and other peripheral circuits, the oscillator must be activated each time before the single-chip microcomputer is brought in operation with them.
Alternatively, the power saving of the single-chip microcomputer is carried out by switching a high-rate mode and low-rate mode. The single-chip microcomputer has the high-rate mode based on a clock signal generated by a high-rate oscillator, and the low-rate mode based on a clock signal generated by a low-rate oscillator, and operates in the low-rate mode to save power except when the high-rate operation is required.
FIG. 11 is a block diagram showing a configuration of a single-chip microcomputer capable of carrying out power saving by switching its mode between the sleep mode, high-rate mode and low-rate mode. In FIG. 11, the reference numeral 100 designates a single-chip microcomputer, 101 designates a CPU, 102 designates a timer, 103 designate a RAM, 104 designates a ROM, 105 designates an interrupt controller, 106 designates an A/D converter, 107 designates an I.sup.2 C bus, 108 designates an input/output port, 109 designates a clock generator, 110 designates a data bus, 111 designates an address bus, 112 designates a control signal line, 113 designates a high-rate oscillator for generating an original high-rate clock signal, and 114 designates a low-rate oscillator 114 for generating an original low-rate clock signal. These oscillators 113 and 114 generate the original clock signals using an external crystal oscillator or ceramic oscillator with high accuracy.
Next, the operation of the conventional single-chip microcomputer will be described.
The single-chip microcomputer 100, with its timer 102, RAM 103, ROM 104, interrupt controller 105, A/D converter 106, I.sup.2 C bus 107, input/output port 108 and clock generator 109 connected to the CPU 101 through the data bus 110, address bus 111, and control signal line 112, executes programs stored in the ROM 104 while storing and reading data to and from the RAM 103, thereby carrying out control by activating the peripheral devices such as the timer 102.
In this case, a system clock signal .phi. generated by the clock generator 109 is required to bring into operation the embedded circuits such as the CPU 101, ROM 104, RAM 103, timer 102, interrupt controller 105, A/D converter 106, I.sup.2 C bus 107, and input/output port 108. The clock generator 109 generates the system clock signal .phi. using the original clock signals oscillated by the external oscillators 113 and 114.
The single-chip microcomputer 100 has the CPU 101 execute a sleep mode instruction to bring itself into the sleep mode by stopping the oscillation of the high-rate oscillator 113 and low-rate oscillator 114 and halting the supply of the system clock signal .phi. to the CPU 101 and the peripheral circuits. To release the sleep mode, an external trigger signal is usually input to recover the supply of the system clock signal .phi. to the CPU 101 and peripheral circuits. In this case, the high-rate oscillator 113 starts its oscillation in response to the external trigger signal, and restarts the supply of the system clock signal .phi. after the oscillation has been stabilized.
The switching between the high-rate mode and low-rate mode is generally carried out by the instruction of the CPU 101. For example, when the high-rate operation becomes unnecessary, the following steps are taken to achieve switching from a first state, in which both the high-rate oscillator 113 and low-rate oscillator 114 are oscillating and the system clock signal .phi. is supplied from the high-rate oscillator 113 to carry out the high-rate operation, to a second state, in which the oscillation of the high-rate oscillator 113 is stopped and the system clock signal .phi. is supplied from the low-rate oscillator 114 to save power.
(1) The CPU 101 issues a command to have the low-rate oscillator 114 supply the system clock signal .phi..
(2) The CPU 101 issues a command to stop the high-rate oscillator 113.
Reversely, switching from the second state to the first state is carried out through the following steps to have the high-rate oscillator 113 supply the system clock signal .phi..
(3) The CPU 101 issues a command to restart the oscillation of the high-rate oscillator 113.
(4) The CPU 101 waits until the oscillation of the high-rate oscillator 113 is stabilized.
(5) The CPU 101 issues a command to have the high-rate oscillator 113 supply the system clock signal .phi..
The conventional data processor with the foregoing configuration has a problem, in the case of saving power using the sleep mode, in that it must wait for a few hundred microseconds to a few milliseconds until the oscillator has been stabilized after releasing the sleep mode, which causes an idle time.
It has a similar problem, when switching the mode between the high-rate mode and low-rate mode, in that it must wait for a few hundred microseconds to a few milliseconds until the high-rate oscillator has stabilized its oscillation after it started the oscillation, which also involves an idle time. Thus, to operate the A/D converter and other peripheral circuits at the high rate, it is unavoidable that some idle time occurs because they cannot operate at the high-rate while the high-rate oscillator 113 is being stopped, and hence it must be switched to the high-rate mode each time to bring them into operation.
This presents another problem in that effective power saving is difficult. For example, before shifting into the high-rate mode, it is often desirable to operate only the A/D converter or peripheral circuits at the high-rate with keeping the remaining components like the CPU in the sleep mode or in the low-rate mode. To operate the A/D converter or peripheral circuits in the conventional system, however, it is necessary for the CPU to release the sleep mode or to switch into the high-rate mode, which inevitably brings the remaining components into operation at the high-rate. This results in an increase in consumption current due to the remaining components, thereby hindering the effective use of the A/D converter and other peripheral circuits from the viewpoint of power saving.